The present invention relates generally to semiconductor device processing and, more particularly, to a semiconductor transistor gate structure having an independently tailored vertical doping profile.
Polycrystalline silicon (polysilicon or poly-Si) has become the preferred material for gate electrodes in MOSFET structures. In particular, polysilicon is advantageous over metal gate electrodes in that it can withstand much higher subsequent processing temperatures before eutectic temperatures are reached. In addition, polysilicon is readily deposited on bulk silicon or silicon dioxide (SiO2) using low pressure chemical vapor deposition (LPCVD).
State of the art MOSFET transistors are fabricated by depositing a gate stack material over the gate oxide and substrate. Lithography and etch processes are used to define the poly-Si gate structures, and both the gate structure and silicon substrate are then thermally oxidized. Subsequently, source/drain (S/D) extensions and halos are implanted. Such implants are typically performed through the use of spacers in order to create a specific distance between the gate and the implanted junction. In certain instances, the S/D extensions for an NFET device will be implanted without spacers, while the S/D extensions for a PFET device will be implanted with spacers present. A thicker spacer is typically formed before the S/D extensions have been implanted. Thereafter, deep S/D implants are then performed with the thicker spacers present. High temperature anneals are then performed in order to activate the junctions.
As the drive toward integrating more active devices on a single integrated circuit necessitates the fabrication of increasingly small MOSFET structures, the resistance of the MOSFET gate becomes a limiting factor in device speed. Thus, it is beneficial to use materials with the lowest possible sheet resistivities for making contact with the polysilicon gate structure. To this end, it is well known that refractory metal silicides may be readily formed on polysilicon MOSFET gate structures by using conventional sputtering, deposition, and annealing processes. The refractory metal silicides have relatively low sheet resistivities after annealing, and also form low resistance ohmic contacts with commonly used interconnect metals. Accordingly, once the junctions are activated by the high temperature anneal, both the S/D regions and the top portion of the gate are silicided.
In order to both sufficiently increase the poly-Si activation and minimize poly-Si depletion effects, the gate is doped at a relatively high dopant concentration. Unfortunately, when the gate is heavily doped, the high dopant concentration can also adversely affect silicidation on the gate, particularly as the gate line width decreases below the 0.1 xcexcm threshold. Because proper silicide formation is integral in achieving low resistance gates (and therefore reduced signal propagation delay), it is also desirable to have a gate structure wherein the bottom portion of the gate is heavily doped to minimize the poly-Si depletion effects while, at the same time, the top portion of the gate is more lightly doped for proper silicide formation. However, with current device processing methods, even if a separate, lightly doped implant is performed for the top portion gate, the subsequent annealing process causes a redistribution of the dopant within the gate, thereby resulting in a relatively uniform vertical dopant concentration.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a gate structure for a semiconductor transistor. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
In another aspect, a MOS transistor device includes a source diffusion region and a drain diffusion region. A gate stack structure disposed upon a gate dielectric, the gate stack structure further including a lower polysilicon region doped at a first dopant concentration, a conductive barrier layer disposed on the lower polysilicon region, and an upper polysilicon region disposed on the conductive barrier layer. The upper polysilicon region is doped at a second concentration that is different than the first concentration, and wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
In yet another aspect, a method for forming a gate structure for a semiconductor transistor includes forming a lower polysilicon region on a gate dielectric layer. The lower polysilicon region is implanted with a dopant at a first dopant concentration. Then, a conductive barrier layer is formed upon lower polysilicon region, and an upper polysilicon region is formed upon the conductive barrier layer. The upper polysilicon region is implanted at a second dopant concentration, said second concentration being lower than said first concentration.